Technical Field
The present invention relates to semiconductor processing, and more particularly to methods and devices for a dual liner with improved contact resistance and reduced pinch off.
Description of the Related Art
In complementary metal oxide semiconductor processing (CMOS), n-type and p-type devices are formed together. These devices may share processing steps at certain points in a workflow but need to be processed separately in others. One process where the n-type and p-type devices are processed separately includes dual liner integration for forming liners for self-aligned contact (SAC) formation.
A first liner for n-type field effect transistors (NFETs) is applied over both NFETs and p-type field effect transistors (PFETs). The first liner is then removed from the PFETs followed by a second liner over the PFETs and the NFETs. With shrinking contact size, the NFET gets pinched off due to the presence of both liners. Pinched off means that the contact hole gets blocked preventing the contact hole from being filled with contact material. This also increases contact resistance and could result in device failure.